The present invention relates to a semiconductor memory apparatus.
In the semiconductor memory apparatus, it has hitherto been practice to provide spare lines and spare memory cells in expectation of occurrence of a defect in a memory cell or word line.
FIG. 5 is a schematic diagram of a row selection circuit in a prior art semiconductor memory.
In the semiconductor memory apparatus described in, for example, JP-A-4-143999, a redundancy select circuit of row direction is provided which is comprised of a main decoder and a section decoder as shown in FIG. 5. The row selection circuit of FIG. 5 comprises circuits including a memory cell array connected to fore ends of subword lines SWL1 to SWL256, a redundancy cell array connected to fore ends of spare subword lines SSWL1 and SSWL2, main word lines MWL1 to MWL64, section selection lines SSL1 to SSL4, spare main word lines SMWL1 to SMWL2, a main decoder for selecting one main word line in accordance with a first row address, a section decoder for selecting one section selection line in accordance with a second row address and a section address, section word drivers SWD for selecting one row on the basis of potential on the main word line and section selection line, a spare decoder and spare section drivers SSD.
With this construction, in the event that a row address selected on the basis of first and second row addresses is an address of a defective cell row, the spare main word lines SMWL1 and SMWL2 are selected by the spare decoder and one row of the redundancy cell array is selected by a spare section driver SSD. Through this, the number of redundancy cell arrays in the semiconductor memory apparatus can easily be decreased to one for one by the spare subword lines SSWL1 and SSWL2.
With the above construction, however, in the event that a plurality of memory blocks become defective at a time by a plurality of defective addresses in a memory array in which one memory block is constructed of a plurality of memory cells, a great number of main word lines of memory blocks associated with the individual defective addresses are needed and when these main word lines are laid, the number of main decoders increases to raise the ratio of occupation of these word lines in the chip area and as a result, the yield is decreased.
If one main decoder is laid for the plurality of word lines of the memory block comprised of the plurality of memory cells to relatively simplify the construction, then one main word line per one row (one cell) will be needed in the prior art layout of redundancy line, thus making it difficult to arrange the decoder.
Further, when replacement is carried out memory block by memory block, even many sound word lines are replaced with an added spare word line group, raising a problem that the replacement efficiency of redundance is decreased.